Characterization of the H2M Monolithic CMOS Sensor
Authors
Rafael Ballabriga
Eric Buschmann
Michael Campbell
Raimon Casanova Mohr
Dominik Dannheim
Jona Dilg
Ana Dorda
Ono Feyens
Finn King
Philipp Gadow
Ingrid-Maria Gregor
Karsten Hansen
Yajun He
Lennart Huth
Iraklis Kremastiotis
Stephan Lachnit
Corentin Lemoine
Stefano Maffessanti
Larissa Mendes
Younes Otarid
Christian Reckleben
Sébastien Rettie
Manuel Alejandro del Rio Viera
Sara Ruiz Daza
Judith Schlaadt
Adriana Simancas
Walter Snoeys
Simon Spannagel
Tomas Vanat
Anastasiia Velyka
Gianpiero Vignola
Håkan Wennlöf
Abstract
The H2M (Hybrid-to-Monolithic) is a monolithic pixel sensor manufactured in a modified \SI{65}{\nano\meter}~CMOS imaging process with a small collection electrode. Its design addresses the challenges of porting an existing hybrid pixel detector architecture into a monolithic chip, using a digital-on-top design methodology, and developing a compact digital cell library. Each square pixel integrates an analog front-end and digital pulse processing with an 8-bit counter within a \SI{35}{\micro\meter}~pitch.
This contribution presents the performance of H2M based on laboratory and test beam measurements, including a comparison with analog front-end simulations in terms of gain and noise. A particular emphasis is placed on backside thinning in order to reduce material budget, down to a total chip thickness of \SI{21}{\micro\meter} for which no degradation in MIP detection performance is observed. For all investigated samples, a MIP detection efficiency above \SI{99}{\%} is achieved below a threshold of approximately 205 electrons. At this threshold, the fake-hit rate corresponds to a matrix occupancy of fewer than one pixel per the \SI{500}{\nano\second}~frame.
Measurements reveal a non-uniform in-pixel response, attributed to the formation of local potential wells in regions with low electric field. A simulation flow combining technology computer-aided design, Monte Carlo, and circuit simulations is used to investigate and describe this behavior, and is applied to develop mitigation strategies for future chip submissions with similar features.
